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Jay Trivedi
Currently working as an ASIC Chip DV lead and with over 10 years of experience in the semiconductor domain, I am currently driving all SoC & IP verification efforts at Edgecortix. I have experience in setting up a verification environment in UVM/Verilog/System Verilog from Scratch. Decent experience in developing full verification infrastructures around various tools such as Xcellium, Vivado, Spyglass Lint, and various simulators in multi-language platforms Perl, TCL, and Python. Hands-on experience and good in debugging RTL, Simulations, Synthesis/Place-Route Issues. Also tracking IP releases and maintaining release quality in check. Apart from technicals, I have good communication skills and decent experience in handling and maintaining cross-company relations and opening new business communications with various different companies. My communication skills have led to good business deals with various different companies which have benefited the startups that I've worked for. I am an adept multi-tasker who thrives in a high-pressure work environment.
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